1. Technical Field
The present invention relates, in general, to computing or processing systems, and more particularly, to the dynamic configuration or reconfiguration of such a system. Still more particularly, the present invention relates to methods, systems and program products for facilitating hotplugging of multiple adapters into a system having at least one bus with multiple hotplug slots, and to the transparent obtaining of an optimum bus speed responsive to, and independent of an order of, connection of the multiple hotplug adapters to the multiple hotplug slots.
2. Description of Related Art
The peripheral component interconnect (PCI) specification introduced by Intel Corporation defines a high-performance local bus architecture that supports installation of PCI-compliant expansion cards. The PCI standard has evolved over a period of years to support a wide assortment of system and hardware component capabilities. As used herein, “hardware components” can mean any part of a processing system and may include data storage devices, communication devices, etc. “Hardware adapters” are, for example, hardware components implemented on an adapter card installed on an expansion slot. Hardware adapters can usually be easily moved or replaced while other hardware components may be permanently coupled (e.g., soldered) to the processing system.
Whereas the original PCI bus standard, herein referred to as “conventional mode”, limits bus clock frequency either to 33 MHz or 66 MHz, newer PCI-X hardware adapters, operating in “PCI-X mode”, are today capable of bus communication at 66 MHz, 100 MHz or 133 MHz. Available PCI-compatible hardware adapters support either 32-bit wide and 64-bit wide versions of the PCI bus and operate at a variety of supply voltages (e.g., 3.3V and 5V). Future expansions and revisions of the PCI architecture may include higher supported clock speeds, wider buses, or double-data rate modes of operation, which will result in an even wider array of possible system configurations.
Despite the wide array of implementations, compatibility has been maintained between devices implementing different PCI bus versions. For example, PCI buses are programmed to operate at the fastest common speed or mode that all hardware components on the bus can support. Hardware components restrict their speed or mode in the presence of buses or hardware components that are not capable of faster operation. In general, hardware components having different characteristics that are coupled to the same PCI bus will function properly, but the performance of the faster hardware components will be degraded due to the lower bus frequency dictated by the slower hardware components. “System performance” or “performance” can be measured, for example, as the throughput of a processing system or the total number of users the processing system can currently support.
The performance of hardware devices on the PCI buses within a system can be a significant factor in the overall performance of the system. Accordingly, the present invention recognizes that configurations that prevent devices from operating at their maximum capability should be avoided. For example, with conventional hotplug approaches, careless ordering of placement of hotplug adapters on a bus can result in significant performance degradation. The processing system may continue to function despite the less-than-optimum hardware component configuration, so problems with the configuration may only be evident during special circumstances (e.g., intervals of peak demand of the processing system resources).
Consequently, since system administrators and other computer users are typically not experts on PCI bus specification, there is a growing demand for a facility for hotplugging multiple adapters onto one or more buses of a system and transparently obtaining an optimum configuration for each bus responsive to, and independent of an order of, the addition of hotplug adapters.